1. Field of the Invention
This invention relates generally to the data processing apparatus and, more particularly, to the specialized high performance processor units generally referred to as digital signal processing units. The invention relates to the transfer of signal groups between the various components of the digital signal processor.
2. Background of the Invention
Digital signal processing units have been developed as specialized data processing units. These units are optimized to perform routine, albeit complex, operations with great efficiency. For many applications, the computations need to done in as close to real time as possible. In order to achieve the computational speed required of the digital signal, the digital signal processing units are optimized to perform the specified processing operation(s) with great efficiency. In addition, many of the functions that would be performed by a general purpose processing unit are eliminated or the funtionality performed outside of the core processing unit.
Referring to FIG. 1, a digital signal processing unit 1, according to the prior art, is shown. A first digital signal processor 10 includes a core processing unit 12 (frequently referred to as a processing core), a direct memory access unit 14, a memory unit or memory units 16, and a serial port or serial ports 18. The memory unit 16 stores the signal groups that are to be processed or that assist in the processing of the signal groups to be processed by the core processing unit 12. The core processing unit 12 performs the bulk of the processing of signal groups in the memory unit 12. The direct memory access unit 14 is coupled to the core processing unit 12 and to memory unit 16 and mediates the signal group exchange therebetween. The serial port 18 exchanges signal groups with components external to the digital signal processing unit 1. The core processing unit 12 is coupled to the serial port 18 and to the memory unit 16 and controls the exchange of signal groups between these components.
The digital signal processor is typically designed and implemented to have limited functionality, but functions that must be repeated and performed rapidly. The fast Fourier transform (FFT) calculation and the Viterbi algorithm decoding are two examples where digital signal processors have been utilized with great advantage. To insure that the digital signal processors operate with high efficiency, the core processing is generally optimized for the performance of limited processing functions. Part of the optimization process involves the off-loading, to the extent possible, any processing not directed toward the optimized function. The exchange of signal groups involving the core processing unit and the memory unit has been assigned to the direct memory access unit.
The digital signal processor has assumed greater processing responsibilities. Not only does the need for speed remain undiminished, but a simultaneously, the requirements to exchange signal groups with a wider variety of external apparatus have arisen. For example, in a digital signal processing unit having multiple digital, signal processors, it is frequently necessary to communicate between the digital signal processors that are part of the same digital signal processing unit. While this communication can be performed through the serial port, this mode of operation has proven cumbersome and slow. Similarly, a host microcontroller requiring the exchange signal groups with the digital signal processor can similarly use the serial port to communicate with a digital signal processor at the expense of operational efficiency. In addition, the addressing modes that are implemented both in the memory unit (e.g., the circular buffer mode) and in the serial port (e.g., the sorting mode) have become increasingly complex. All of this increasing computational complexity has the potential to undermine the performance of the microcontroller.
A need has therefore been felt for apparatus and an associated method having the feature that the transfer of signal groups between components of a digital signal processor is accomplished without the active participation of, but under the control of the core processing unit. It would be another feature of the apparatus and method to place the control of the transfer of signal groups in the digital signal processor in the direct memory access controller. It would be still another feature of the apparatus and associated method to have flexibility in coupling the source and destination components involved in the transfer of signal groups. It would be yet another feature of the apparatus and associated method to prioritize and to prevent conflicts in the transfer of signal groups within the digital signal processing unit. It would be still further feature of the apparatus and associated method to permit the transfer of signal groups with components external to the digital signal processor. It would still another feature of the apparatus and associated method to provide flexibility in the addressing modes available to the direct memory access controller.
The aforementioned and other features are accomplished, according to the present invention, by a direct memory access controller that has programmable channels, a flexible addressing unit and apparatus for avoiding conflict between requested signal transfers. The direct memory access controller assumes the responsibility for the exchange of data groups between the serial port and the memory unit, thereby relieving the core processing unit of this operational responsibility. In addition, by adding a host port interface unit to the digital signal processor, parallelly formatted signal groups can be exchanged with external components, particularly a microcontroller. A processor to processor interface unit provides for the exchange of signal groups between digital signal processors that are part of the same digital signal processing unit. The direct memory access controller includes context registers available to the core processing unit that provide the core processing unit with over all control of the transfer of signal groups within a digital signal processor. The direct memory access controller includes a plurality of programmable channels that can couple the source component to the destination component. The direct memory access controller includes an arbitration unit so that the requests for access to the channels can be prioritized and conflicts avoided.